Dr Vladimir Ivchenko is an Electronics and FPGA Design Engineer who specialises in the development and design of quality, robust electronics systems. After a career span of over twenty years during which he researched and designed ASIC and FPGA based systems for Automotive, Chemical,Transport, Energy and Instrumentation industries Vladimir founded VLA Solutions Ltd.

Download Vladimir's CV:

Concise CV:

Dr Vladimir Ivchenko

email: This email address is being protected from spambots. You need JavaScript enabled to view it.

Linkedin: https://uk.linkedin.com/in/vladimir-ivchenko-4061aa55

Web: www.vlaresearch.com , Phone: +44-(0)798-1127-585

SUMMARY

More than 20 years of diverse experience in FPGA and custom ASIC design and verification, programming for various application specific tasks
Automotive, Oil & Gas, Energy, Chemical industrial environments
14 years of ultrasonic instrumentation electronics developments
Well experienced in full expansion circle of electronics including concept, analogue/digital design, PCB, casing, manufacturing and commercialisation
Developed theoretical and practical approaches for noise immune measurement systems and for high resolution ultrasonic imaging, commercialised through licensing and patenting
In-depth knowledge of microelectronics
Excellent skills in ultimate HDLs including structural, RTL and behavioural coding
Experienced in Digital Signal Processing systems and protocols controllers development
Well versed in image processing algorithms
Strong knowledge of testing technics
Hold two patents
University level instruction experience (Programming, Ultrasonic instrumentation, Circuit technique, Logic Design and Verilog/VHDL)

SKILLS

Programming Languages : C, C++, C++ MFC, Visual Basic, Java, Perl, Linux Shell Script, Tcl, strong in Matlab and LabView
Hardware Description Languages : Expert knowledge of VHDL, experienced in Verilog, SystemVerilog DPI, AHDL, VHDL-VITAL, EDIF, SDF
EDA Tools : MatLab, LabView, SPICE, FPGA tools Xilinx Vivado and SDK, ISE, System Generator, Xilinx ChipScope Pro, Lattice Diamond, Clarity Designer and Deployment, Altera Quartus, Microsemi Libero, Mentor Graphics HDL Designer and ModelSim / QuestaSim, Leonardo Spectrum HDL, Renoir HDL, Altium PCB, Eagle PCB, Cadence IC tools, Tanner IC tools, Synopsys PCI-X FlexModels, Keil uVision, Analog Devices VisualDSP++, Eclipse
Embedded Programming: Xilinx Zynq Ultrascale+, MetalLib, Analog Devices Blackfin DSP, ARM Cortex, Microchip, Cypress EZ-USB Microcontrollers
Architectures: Structural, Data Flow, FSM, Design for Test, FIR architectures for DSP, FFT, QAM, Adaptive LMS filters, Serdes, Proprietary instrumentation architectures: Pseudo Random Binary Sequence-based (PRBS), Arbitrary Interleaved Sampling (AIS), On-The-Fly Coherent Averaging, 128-channel Ultrasonic Imaging System, custom DAC
Technologies : FPGA including timing closure, ASIC, microcontrollers, AXI bus, DMA, DDR2, DDR3, SRAM, eMMC, IoT, SoC, Docker
Electronics : Digital, Analogue and mixed signal
Interfaces : Sondex telemetry, Ethernet, MIPI, SCI-2, DSI, USB, PCI, LVDS, JTAG, SPI, I2C, UART, CAN, EPP, Manchester, High speed custom interfaces
Version Control Systems : Serena, SVN, GitHub
Requirements Management: IBM Rational DOORS
Operating Systems : Unix HP-UX, MS Windows, Linux, embedded PetaLinux, GE Edge OS
Technical writing : Seasoned documentation writer

EDUCATION

1997 Ph.D. in Electrical and Electronic Engineering, State University, Russia

1993 BS in Electrical Engineering, GPA 4.94 (5 point scale), State University, Russia

PROFESSIONAL EXPERIENCE

October 2014 – Present, VLA Solutions Ltd, UK

Consultant, Electronics and Firmware Design Engineer, Technical Director

Project: PCIe Radio Receiver 100kHz to 18GHz

Client: CRFS, UK, USA

The PCIe Radio Receiver has been made to be capable for 24/7 monitoring of RF threats. Used in arrays it has been helping the European Space Agency stay in control of the RF spectrum at their Deep Space Antenna sites across the world. The Radio communicates with host system via 4-lanes PCIe interface.

Resolved bugs and timing issues for Xilinx Kintex FPGA project
Migrated project from Xilinx ISE to Vivado
Delivered comprehensive testbench based on SystemVerilog DPI for FPGA-uC co-simulation
Developed schematic and PCB with PCIe switch for i7 processor carrier board

Project: Ultrasonic Acquisition Platform for Non-Destructive Testing

Client: Tribosonics Limited, UK

The system and verification environment are based on Xilinx SoC Zynq and Spartan 6 FPGAs. The platform’s Spartan 6 FPGA controls the acquisition operation, runs on-the-fly averaging, calculates CRC, implements the custom on board FIFO, packs the data frames and communicates with external processor via Smart External Memory Controller interface.

Led development of system architecture
Developed Xilinx Spartan 6 FPGA firmware for the platform and Xilinx Zync-7010 FPGA firmware for testing environment
Implemented software for embedded Linux testing the Acquisition Platform
Discovered problems with schematic, PCB and components selection and assisted the client with required corrections

Project: Platform for Oil Wells Monitoring

Client: Baker Hughes, a GE Company, UK, USA

This is a new generation of surface panel for wireline logging. The tool is based on multicore SoC Xilinx FPGA Zynq Ultrascale+. The system utilizes extensive digital signal processing (DSP) to communicate with down hole equipment at 33,000 feet depth and with computerized control terminals. Embedded Linux (GE Edge) runs in SoC FPGA and controls interaction of all components.

Assessed telemetry path and developed DSP environment
Analysed implementation complexity and developed scalable architectures for FPGA fabric and for embedded software, assigned functionalities to SoC processor cores
Developed FPGA firmware, standalone and embedded Linux applications, Linux drivers, and Linux-to-standalone interface
Technologies worked closely with in this project: SoC FPGA, SERDES, ADC, DAC, DPOT, EEPROM, Embedded Linux, Petalinux, OpenAMP, LibMetal, Docker, Dispatcher SW architecture, QAM, FIR, IIR, FFT, LMS Adaptive Filter, AXI bus, DMA, Sondex telemetry interfaces, Ethernet, USB, LVDS, JTAG, SPI, I2C, UART,
Tools used in this project: Xilinx Vivado and SDK, ModeSim, Matlab, Altium PCB, Eclipse, Oscilloscope, Logic Analyser

Project: Support for multiple projects in Oil Wells Monitoring

Client: Baker Hughes, a GE Company, UK, USA

More than ten new and updated oil wells monitoring products were introduced in considered time. The units are based on various FPGAs and microcontrollers. Supporting consultancy included critical modifications to existing products and development of unique functionality for new devices.

Developed firmware for Altera and Microsemi FPGAs
Developed firmware for microcontrollers from Analog Devices, Cypress, Microchip and NXP
Technologies worked closely with in this project: uC, FPGA, ADC, DAC, DPOT, EEPROM, FIR, DMA, Sondex telemetry interfaces, USB, JTAG, SPI, I2C, UART
Tools used in this project: Altera Quartus, Microsemi Libero, ModeSim, Eclipse, Oscilloscope, Logic Analyser

Project: Radar processor for Advanced Driver-Assistance Systems Data Distribution Services (ADAS DDS)

Client: EnSilica Limited, UK

This project is dedicated to the automotive industry. The processor post-process Radar data and detects targets and their associated range, speed, azimuth and elevation. System encompasses two FPGAs (Xilinx and Lattice) and comprises SCI-2 and LVDS protocol controllers.

Assessed data path and developed interface for radar RF digital data
Developed firmware for Xilinx and Lattice FPGAs
Implemented control C software performed in embedded Linux environment and commanding the radar
Implemented software programming Lattice FPGA via Xilinx Zynq FPGA SPI interface

Project: Central Driver Assistance System

Client: Valeo, Germany

The project is devoted to automotive industry. The System collects information from variety of sensors to assist a driver to the high safety and convenience standards. The sensors include Ultrasonic, Long and Mid-Range Radar, Video Camera, Laser Scanner and Satnav.

Managed and analysed software specifications using IBM Rational DOORS
Developed test cases based on Java and Eclipse environment
Provided consistency of the software and tests by using Serena Dimensions and CDA ALM for versions management
Executed software and real time hardware co-simulation tests, performed constraints and performance analysis, reported tests issues

Project: Electronic Platform for Ultrasonic Measurements

Client: TSK Solutions Ltd, UK

Customer needed an OEM platform for ultrasonic process monitoring and non-destructive testing. Hardware: Low-noise variable gain amplifiers, 350 MHz dual ADC, FPGA Xilinx Artix7, DDR3, USB controller, low- and high-voltage DC/DC converters, high-speed ultrasonic drivers, temperature sensor. Firmware: FPGA VHDL. Software: C++ API DLL. Tools: Xilinx ISE and Vivado, Altium PCB, Microsoft Visual Studio.

Consulted customer on system architecture and specifications
Developed schematic and PCB of the system
Developed FPGA firmware
Developed API DLL, User Interface software (C++, MFC)

Project: Software platform for automatic generation of VHDL firmware and C++ code for DLL API and MFC user interface

Due to the frequent need for re-customisation of FPGA platform firmware and software interface comprising API DLL and User Interface I developed a MS Excel Visual Basic software for specification and automatic generation of C++ code handling all interaction with FPGA-based platform, implementing components of MFC User Interface and also for generation of VHDL code fitting to the set specifications. The software and FPGA firmware implement EPP interface to digital core.

Project: Car Contour Recognition System

Client: Eeins GmbH, Germany

This project included development of hardware and software for car contour recognition system.

The system is used in automotive manufacturer’s laboratory for characterisation of ultrasonic parking assistance system.

Developed an image and car contour recognition LabView software
Designed hardware components for the system
Consulted customer for installation, testing and debugging the system

August 2015 – September 2016, Tribosonics Ltd, UK

Electronics Design Engineer

Project: Ultrasonic Digital Acquisition Wireless Communication Module IoT Node

The goal of the project was to develop a battery powered system with 8 years active life for ultrasonic measurements with possibility to track position and transmit measurements by on-board 3G/GPS module. Hardware: FPGA Xilinx Spartan3, ADC, low-noise amplifiers, DC/DC converters, power management, 3G/GPS module, PIC microcontroller, flash memory, USB interface, UART, temperature sensors, ESD, CE certification. Firmware: FPGA, Microchip PIC microcontroller.

Led architecture design and specifications issue
Developed schematic and PCB of the system and prototypes using Altium Designer PCB
Assisted in FPGA design amendments in Xilinx ISE
Designed C firmware for on-board PIC microcontroller with Microchip MPLAB X IDE: USB interface, power management, data path, test cases.
Procured and managed manufacturing of prototypes and the final system PCB

July 2012 – October 2014, Digusonic, UK

Senior Electronics Design Engineer

Project: High Sensitive Automotive Sensor Platform for Parking Assistant System

I achieved 4x increase of distance range of industrial 50 KHz automotive sensor by employing PRBS approach. Hardware: Low-noise amplifiers, ADC, FPGA Xilinx Spartan6, USB controller, low- and high-voltage DC/DC converters, high-speed ultrasonic drivers. Firmware: FPGA VHDL. Software: C++ API DLL. Tools: Xilinx ISE, Xilinx System Generator, Eagle PCB, Microsoft Visual Studio, Matlab. The system was patented.

Developed high sensitive architecture utilising Pseudo Random Binary Sequence (PRBS) and cross-correlation processing. Tools: Matlab, Simulink, Xilinx System Generator.
Designed FPGA firmware in Xilinx ISE
Designed MFC User Interface
Designed C API DLL. Tool: Microsoft Visual Studio
Lead preparation of patent EP 2799905 A1 “High Sensitivity Apparatus For Car Parking Ultrasonic Sensors And Method Thereof”

Project: Custom USB interface to FPGA

The aim of the project was to develop an USB interface for ultrasonic instrumentation electronics that implements data transfers and FPGA programming via USB.

Tools: Xilinx ISE, Xilinx ChipScope Pro, Microsoft Visual Studio

Co-ordinated and managed development of windows driver and USB controller firmware
Developed two USB interface components: FPGA firmware and API software to communicate with FPGA-based electronics
Designed FPGA test firmware, tested and debugged software and directed software engineers to correct mistakes

March 2004 – August 2015, University of Nottingham, UK

Research Fellow

EPSRC, RCNDE grants

Project: 128-channels Compact Ultrasonic Array Controller with On-Board Image Processor

The project aims on establishing theoretical and practical approaches for development of challenging compact electronics for ultrasonic array controller and imaging processor mounted in the housing of 128 transducer array. High resolution ultrasonic image is obtained by Full Matrix Capture algorithm and processed by Total Focusing Method by the on-board electronics. The system utilises the Pseudo Random Binary Sequence (PRBS) excitation and post-processing technique to attain sensitivity in materials with high attenuation.

I estimated the technology and architectural factors influencing the system effectiveness and developed an architectural model than allowed to derive optimal system architecture in the performance-cost-size basis.

Hardware: Two Xilinx Spartan6 FPGAs, USB controller, DDR2, front-end ADC, Hitachi HV pulsers, DC/DC converters. Firmware: VHDL FPGA. Software: C API DLL, MFC C++ User Interface. Tools: Matlab, Simulink, Cadence Encounter RTL Compiler, Xilinx System Generator, Xilinx ISE and Vivado, Microsoft Visual Studio

Assessed ASIC and FPGA implementations of controller using Cadence Encounter and Xilinx ISE
Developed FPGA-based system architecture and schematic
Designed API DLL, User Interface software
Proposed the on-the-fly architecture for PRBS cross-correlation
Proposed optimised compact 2D ultrasonic image processing architecture
Designed PCB, FPGA firmware, DDR2 interface, software API and user interface control software
Developed algorithms for system self-calibration
Procured and managed the system manufacturing
Presented the system on two RCNDE Technology Readiness Workshops

Project: Wide Dynamic Range Ultrasonic Spectrometer

This project aroused as an implementation of my previous scientific research to obtain a super-sensitivity of ADC well below the quantisation level and to achieve a tolerance to high levels of noise. This was used in novel Ultrasonic Spectrometer capable to measure 170 dB of dynamic range signals. Results of the project were commercialised and licensed to industry.

Developed theoretical and practical approaches to design high sensitive, noise tolerant measurement systems
Designed the ultrasonic system capable to measure signals in range of nanovolts in presence of thousands times higher noises and sampled by the ADC with quantisation level of a half of millivolt.
Designed schematic and PCB for the system. Tool: Eagle PCB
Designed FPGA Spartan3 firmware for partner development board. Tool: Xilinx ISE
Developed the API software to integrate the electronics in LabView, Matlab and C++ GUI
Published results in high calibre journals and presented on conferences

Project: ACPD system for ageing monitoring of high-pressure high-temperature constructions

The project was intended to employ Alternative Current Potential Drop (ACPD) to control condition of high-pressure pipes. I participated in development of a controllable current source. Tools: LTspiceIV, Eagle PCB

Modelled and simulated the current source in SPICE
Designed PCB, manufactured and debugged the current source
Procured and managed a production of rest units of the system
Consulted collaborators for integrating the current source in the complete system

Project: High Resolution Time Domain Ultrasonic System

The project was aimed on development of architectural principles for building ultrasonic measurement system with very high time resolution. I developed an Accurate Interleaved Sampling and on-the-fly averaging architecture. High 1.5 GHz effective sampling frequency was achieved with single 50 MHz ADC. The system was implemented on Xilinx FPGA development board XtremeDSP Development Kit Virtex-2.

Designed novel Arbitrary Interleaved Sampling architecture
Developed FPGA firmware using Matlab, Xilinx System Generator and ISE
Debugged two clock domains issues with Xilinx ChipScope Pro
Designed Matlab GUI for measurement device and data processing (LP filtering, averaging, zero crossing etc.)
Presented results on conference and published in IEEE journal.

Project: Custom Ultrasonic Front-End ASICs

I developed two integrated circuits: single channel and sixteen channels mixed analogue/digital custom ASICs in Cadence design environment. I procured ICs manufacturing by Europractice and designed custom PCBs for ultrasonic measurement system. Tools: Cadence Virtuoso Layout, Spectre, ADE, Encounter, Eagle PCB.

January 1999 – February 2004, Taganrog State University, Russia

Senior Research Associate

Project : Static RAM Generator

The goal of the project was to design C++ software, circuits, topologies, electrical models, design methodologies and program product for automatic generation of parameterized static RAM based on a custom technology.

Designed the circuits of SRAM
Performed extraction of SPICE equivalent circuits of SRAM topology using Tanner Ledit Pro
Simulated the extracted circuits with Tanner T-Spice Pro and corrected the topology to achieve specified functionality

Project : High Speed 2D FIR hi-pass and low-pass video filters

The goal of the project was to implement the custom image processing filters. The target technologies were ASIC (AMS). The cores do the fully pipelined data processing. Data conversion is implemented in a controlled window of frame. Video data flow is not steady and can be repeatedly interrupted. There was no provided VITAL (VHDL Initiative Towards ASIC Libraries)-compatible VHDL description for ASIC cells library.

Developed the Design Flow for capture a VITAL-compatible VHDL description of technology specific elements library
Created a full set of functional VHDL descriptions (not VITAL) for target ASIC library (70 cells) by writing and executing Tcl scripts in Leonardo Spectrum
Designed the VITAL (Level 0 and Level 1) descriptions for ASIC library based on prepared functional VHDL descriptions
Created the library hierarchy for designed VITAL cells set in Renoir and ModelSim
Wrote the Perl script to fix the differences in Leonardo and Tanner SDF files and implemented interoperability for Tanner tools and Leonardo Spectrum
Integrated the target ASIC library into the Leonardo Spectrum environment
Synthesized the FIR and targeted it to ASIC AMS-0.8 technology and generated gates timing simulation data in SDF file
Implemented Place & Route ASIC Layout using Tanner Ledit Pro and generated propagation delay timing simulation data in SDF file
Assembled timing data into one SDF file using Leonardo Spectrum
Carried out the Back Annotation simulation of ASIC FIR implementation in ModelSim

Project : Virtual Logical Analyser Built-in Core

The core is to be built into FPGA for debugging a live firmware. This core registers data of test points and screens them through parallel ports. Status information is outputted via serial (Manchester code) port. Core also records predicted data and surrounding them successions. Analyser is controlled through JTAG interface and outputs the recorded data using this interface.

Designed a verification environment using VHDL, ModelSim and HDL Designer
Designed the core description in behavioural and structural VHDL language in Mentor Graphics HDL Designer
Synthesized the core in Leonardo Spectrum and mapped it to Altera Stratix device
Placed and Routed the design in Altera Quartus II and generated SDF timing simulation data
Verified the RTL and post layout netlists for functionality and timing

Project : PCI Bus Controller IP Core

This project is devoted to design the parameterized core of PCI v.2.2 Controller. Full version of core is capable to execute all main PCI transactions in Master and Target modes. User-side interface provides 32-bit-wide data exchange and transactions control.

Designed an improved Verification Environment using Synopsys PCI-X FlexModels, ModelSim and HDL Designer
Adopted FlexModel’s Perl and cmd scripts to port them to Windows 98
Designed the user-side interface models based on VHDL procedures with stimulus and monitors, memory and I/O space models
Wrote the Core verification test plan and test suites
Wrote the VHDL testbenches and tested the PCI Controller
Analysed and documented PCI compliance errors and directed design team to correct them

Project : Uploading to PCI Bus IP Core

The goal of the project was reengineering an Altera AHDL design to Verilog code. The core does all logic including bus interaction and data transfer from chip-side source to PCI bus using FIFO. 8-bit input data are combined in 32-bit words and passed to PCI bus in master mode.

Fixed the project fragments which was written along with Altera AHDL coding defaults
Migrated the project developed in Altera AHDL to Verilog using behavioral (for state machine) and RTL coding in HDL Designer
Wrote monitors and stimulus models to automate the verification process in ModelSim using Verilog and do-scripts
Carried out the functional simulation in ModelSim
Done synthesis in Leonardo Spectrum and targeted circuit to Altera FLEX 10KE device
Carried out timing driven Place & Route in Altera MAX+plusII and generated timing simulation data
Executed the extensive timing simulation with Back Annotating in ModelSim
Documented design specification
Consulted the customer with integrating the core into the higher-level module

Project : Moving Selection Video Core

Moving Selection Core is a part of customized video chip module library. It interacts with two pipelined RAMs to access the consistent frames. The core does scaling and calculates projections of object coordinates changing. To achieve a high processing speed the whole project is realized using pipelines.

Wrote the core simulation models in MatLab and verified the custom test benches
Reported several bugs in the tests and worked with the designers to fix the bugs
Designed a memory interface, the core architecture and coded them using behavioural and structural VHDL
Designed test benches and carried out functional Verification at block level as well as at full core level
Synthesized the circuit using Leonardo Spectrum and implemented the netlist in Altera MAX+plusII targeting to Altera FLEX 10KE device with generating back annotation timing simulation data
Executed the Back Annotated simulation in ModelSim
Wrote Perl-based ModelSim-to-MatLab format translator and executed Verification by checking the differences between VHDL-generated monitors and MatLab model
Participated in integrating the core to the high-level module on customer site

Project : High Speed Video 2D FIR edge-detector

Edge-detector works with video data flow which can be repeatedly interrupted. All data processing modules are pipelined for increasing performance. This FIR uses the cruciform aperture. The main core characteristics like aperture sizes, data width, frame size are adjustable on synthesis phase by using VHDL parameters. Output is a frame with image edges.

Designed the detailed core description on behavioural and structural VHDL in Mentor Graphics Renoir
Verified the custom test benches in MatLab and carried out the functional simulation in ModelSim
Synthesized several variants of circuit modules in Leonardo Spectrum and evaluated the best one
Synthesized the whole core and mapped it in to Altera FLEX device
Placed and Routed the design in Altera MAX+plusII and generated a SDF timing simulation data
Verified the RTL and post layout netlist for functionality and timing

Project : Contrast Adjustment Video Core

This core creates the brightness conversion table based on picture brightness histogram and writes the table into external pipelined memory. Input pictures data are taken from other pipelined memory and processed during reading process (customer requirement). All evaluative coefficients are based on the whole data set.

Installed and adapted CAD FPGA Advantage
Designed the input and output memory interface, the core architecture and coded it using RTL and behavioural (FSM) VHDL
Designed and evaluated through synthesis and Back Annotate simulation several variants of dividers and multipliers and improved core’s processing
Coordinated and submitted with customer the improved core architecture
Designed testing data using VHDL and ModelSim do-scripts and carried out the core functional Verification
Synthesized the circuit by Leonardo Spectrum, placed and routed the design in Altera MAX+plusII and generated timing simulation data
Executed the verification by back-annotated simulation in ModelSim
Documented design specifications

November 1993 – December 1998, Taganrog State University, Russia

Research Assistant

Designed and researched GaAs reconfigurable High Speed and Buffer logic cells.
Designed and researched High Speed GaAs logic cells with supply voltage below Shottky voltage. This type of logic consumes up to two times less power than a conventional logic.
Designed the models, method and C-programs for automatic topology synthesis of the cells.
Patented the GaAs reconfigurable High Speed logic cell.
Designed the modelling method of CMOS circuits based on adaptive RC approach which allows to simulate all types of CMOS circuits with high speed and accuracy; wrote the C-program implementing the modelling method.
Designed the method of high reliability system synthesis using VHDL.
Performed the evaluation of VLSI main properties variation for ASIC, Gate Array and CPLD for multi-technology retargeting.
Performed a review of circuit and technological IC reconfiguration methods for custom researches.
Performed a review of constraints and requirements to logic cells for SoC.
Designed Custom Bus Controller using Gate Array technology. It provided access to global memory for four processors. Designed the schematics using OrCAD, translated the structural view to custom P&R CAD, executed P&R and layout optimization.

TEACHING EXPERIENCE

December 1999 – February 2004, Taganrog State University, Russia

Assistant Professor

Taganrog State University is a famous Russian research and academic organization in electrical and electronics engineering. I lectured programming, electronics and VHDL related courses for students and research institute staff.

My Role:

Lectured VHDL related courses including VLSI design and verification using CAD FPGA Advantage and Altera MAX+ PlusII.
Wrote the book: "Design of VLSI Using VHDL" for use by engineering students.
Contributed to the elective course of VHDL-based design beginnings.
Supervised the graduate projects in Verilog and VHDL-based design of peripherals and signal processing modules. Some were performed using Design For Test methodology
Directed students’ projects in VLSI Digital design and Chip Placing & Routing using HP-UX-based Mentor Graphics tools (Design Manager, Design Architect, QuickSim, QuickHDL).
Carried out the laboratory works for VHDL-based Digital design course.

PROFESSIONAL MEMBERSHIP

Institute of Electrical and Electronics Engineers (IEEE)

PROFESSIONAL TRAINING

2012 What is IP: Protecting your technology: Seminar. University of Nottingham, UK

2011 Altera University Program Training Course. STFC Rutherford Appleton Laboratory, UK

2010 Unplugged Wireless Seminar. Duxford IPW, UK

2010 Embedded System Design with FPGAs using Xilinx tools: Seminar workshop. Rutherford Appleton Laboratory, UK

2009 FPGA design using Xilinx tools and devices. Daresbury Laboratory, Warrington, UK

2008 EDA Tools and Flows For Microelectronics Design: Seminar workshop. Rutherford Appleton Laboratory, UK

2006 Xilinx DSP Workshop, Silica Offices, Stevenage, UK

2002 NI LabVIEW for Instrumentation: Hands-On Seminar. Taganrog, Russia

SELECTED PUBLICATIONS

Richard Challis, Vladimir Ivchenko and Raied Al-Lashi. Ultrasonic attenuation measurements at very high SNR: Correlation, information theory and performance. (AFPAC2012), 2013.
R E Challis and V G Ivchenko, "Sub-threshold sampling in a correlation-based ultrasonic spectrometer," Meas. Sci. Technol, vol. 22, pp. 1-12, Aug. 2011.
A. P. Y. Phang, R. E. Challis, V. G. Ivchenko and A N Kalashnikov, “An Integrated Ultrasonic Correlation Spectrometer”, In: Review of Progress in Quantitative Nondestructive Evaluation, vol 27A, pp 1575-1582,eds D.O. Thompson and D.E. Chimenti, American Institute of Physics, Melville, New York, 2008.
A. P. Y. Phang, R. E. Challis, V. G. Ivchenko and A N Kalashnikov, “A field programmable gate array-based ultrasonic spectrometer”, Meas. Sci. Tech., Vol. 19, pp. 1-13, 2008
R. E. Challis, V. G. Ivchenko, A. P. Y. Phang and C. Chirenda, “Prospects for high density system integration for ultrasonic array transducers”, NDT 2007 conference, British Institute of Non-Destructive Testing, September 2007
V. Ivchenko, A. N. Kalashnikov, R. E. Challis, B. R. Hayes-Gill, “High-speed digitising of repetitive waveforms using accurate interleaved sampling”, IEEE Trans. on Instrumentation and Measurement, vol. 56, Issue 4, pp.1322 - 1328, August 2007
A. N. Kalashnikov, V. G. Ivchenko, R. E. Challis and B. R. Hayes-Gill, “High-Accuracy Data Acquisition Architectures for Ultrasonic Imaging”, IEEE Trans. Ultrasonics, Ferroel., Freq.Control, vol. 54, no. 8, pp. 1596-1605, August 2007.
B.G. Konoplev and V.G. Ivchenko. “Method of High Reliability System Synthesis Using VHDL”, Proceedings of the 1st IEEE International Conference on Circuits and Systems for Communications (ICCSC’02), St. Peterburg, Russia, 27-28 June 2002, pp.404-407.
B.G. Konoplev, E.A. Ryndin, V.G. Ivchenko. “Investigation of FPGA, Gate Array and ASIC realizations of VLSI”, Proceedings of Higher Education. Electronics, pp.81-87, N1, 2000.
V.G. Ivchenko. Design of VLSI Using VHDL. Primer for Students, TSURE, 1999.